1. Field of the Invention
The invention relates to a method for polishing a semiconductor wafer provided with a strained-relaxed Si1-xGex layer.
2. Background Art
Modern applications of microelectronics such as information and communication technology, for example, demand ever higher integration density and ever shorter response times and clock breaks of the underlying microelectronic components. Examples of components are memory cells, switching and control elements, transistors, logic gates and the like. These are produced from substrates composed of semiconductor materials. Semiconductor materials comprise elemental semiconductors such as silicon and occasionally also germanium or compound semiconductors such as gallium arsenide (GaAs), for example. One measure of the switching speed is the mobility of the charge carriers (free electrons, holes). The mobility is the average drift velocity of the charge carriers in the crystal lattice of the semiconductor material relative to the applied electric field (electrical voltage per unit distance). The electron mobility is significantly lower for pure silicon than for GaAs, for example. Nevertheless, silicon is the standard material in microelectronics owing to numerous advantages. Silicon is available expediently, easily and virtually without limit, and it is non-toxic, can be produced very cleanly, can be processed well with high freedom from defects, and has a stable oxide (dielectric). Therefore, there is a desire to realize particularly fast components likewise on the basis of silicon technology.
For a given material, it is possible to increase the charge carrier mobility only by artificially altering the properties of the crystal lattice. It is known from theoretical investigations that, in particular, a strain of the crystal lattice (extension, distortion) increases the mobility. The average atomic spacing (lattice constant) of germanium, which is homologous with respect to silicon, is approximately 4% greater than that of silicon. A silicon crystal with incorporated germanium atoms therefore has a higher lattice constant than pure silicon. It is produced by depositing a silicon layer with a germanium proportion that increases slowly with the layer thickness on a defect-free planar and pure silicon starting surface. This is done from the vapor phase by means of thermolysis (“chemical vapor deposition”, CVD) of gaseous germanium-containing precursors, such as GeH4, GeCl4 and GeHCl3, for example, on the surface, or by vapor deposition using particle beams (Molecular beam epitaxy, MBE). This gradient layer having variable Si/Ge stoichiometry keeps down the strain built up on account of the lattice mismatch of silicon and germanium in the crystal during the growth. A further relaxation is achieved by finally depositing a stoichiometrically constant buffer layer with the germanium proportion of the last layer of the Si1-xGex gradient layer. The overall layer construction is referred to as a relaxed layer (“strain-relaxed layer”).
If pure silicon with a small layer thickness is deposited on the relaxed layer, the layer constrains its atomic spacing on the silicon atoms. The deposited silicon layer is laterally extended and is therefore referred to as lattice-strained silicon (“strained silicon”). Components structured in such a strained silicon layer have a charge carrier mobility that is increased according to the degree of strain and thus according to the germanium proportion in the relaxed layer.
A prerequisite for functional components having shorter switching and charge carrier transport times is substantial freedom from defects in the strained silicon layer. It is found that part of the strain of the Si1-xGex gradient layer on account of the lattice mismatch is released in the form of regularly occurring lattice defects. The latter form a network of so-called dislocation defects (screw dislocations) at the piercing points of the growth surface. This defect network leads to regular height modulations of the surface. On the preferred Si(100) substrate, these faults resemble a rhomboidal patching of the surface and are therefore referred to as a “cross-hatch defect pattern”.
The surface of SixGe1-x layers is therefore often characterized by a pattern caused by dislocations and known as “cross hatch”, and must generally be smoothed before one or more further layers can be deposited thereon.
U.S. Pat. No. 6,475,072 and also Sawano et al., Materials Science and Engineering B89 (2002) 406-409, describe polishing methods directed towards smoothing Si1-xGex layers. The methods involve a chemical mechanical polishing (CMP), wherein the semiconductor wafer is moved, with application of polishing pressure, over a rotating polishing plate provided with a polishing pad, while a polishing agent is supplied between the polishing pad and the Si1-xGex layer to be polished. The remaining roughness, measured by AFM (“atomic force microscopy”), is in the best case 5 Å RMS (“root mean square”), in relation to a measurement grid having the area of 10 μm×10 μm. However, a surface polished in this way has disturbing scratches which, owing to their typical widths and depths in the submicron range, are often also referred to as “nanoscratches”. Si1-xGex layers planarized according to known methods are accordingly still too rough to be able to deposit thereon a strained silicon layer for particularly demanding applications which is sufficiently free of defects, smooth, and planar.
DE 102 007 019 565 A1 discloses a method for the single-side polishing of semiconductor wafers provided with a relaxed Si1-xGex layer, comprising polishing a multiplicity of semiconductor wafers in a plurality of polishing passes, wherein one polishing pass comprises a polishing step and at least one of the semiconductor wafers with a polished Si1-xGex layer is obtained at the end of each polishing pass. The semiconductor wafer is moved during the polishing step, with application of polishing pressure, over a rotating polishing plate provided with a polishing pad, and a supply of polishing agent between the polishing pad and the semiconductor wafer. A polishing agent containing an alkaline component and a germanium-dissolving component is supplied.
Particles containing germanium which are left behind if silicon is dissolved under the conditions of chemical mechanical polishing are regarded as the cause of the comparatively high roughness and the nanoscratches after polishing in accordance with the previously known methods. According to DE 102 007 019 565 A1 it does not suffice to remove these particles mechanically, for example in the course of conditioning the polishing pad. Rather, it is necessary to begin dissolving these particles chemically as early as during the polishing.